As is well known, electronic devices, in particular those integrated monolithically, if not carefully protected and sealed can be affected critically by the environmental conditions in which they are placed during assembly and/or during their lifetimes. In particular, the presence of humidity and other contaminating agents can result in the entry of undesired materials into the electrically active part of the device. This generally reduces the reliability of the device and can even irreversibly compromise its operation.
It is therefore crucial, especially for certain applications, to make the best possible provision for protection and sealing of the electrical circuit which is part of the device. For this purpose it is necessary to ensure perfect sealing also at the edge of the device.
For the meaning of edge of a device it should be remembered that a plurality of identical monolithically integrated circuits are formed simultaneously on a single wafer of semiconductor material, commonly monocrystalline silicon, in adjacent prepared areas. The individual devices are spaced and separated by unoccupied cross strips in which the surface of the silicon is left exposed. These strips are typically mutually orthogonal and are known as "scribe lines" and the wafer will be cut through them mechanically to separate the individual devices (the so-called "dicing" process). The edge of a device is thus the peripheral region thereof bordering on the associated scribe line.
After formation of the circuit electrical structures, i.e., of the electrical components, such as, for example, transistors or memory cells and their interconnections, the device is insulated and sealed. Layers of dielectric materials act as electrical and thermal insulators of the conducting interconnection layers and protect the underlying structures of the integrated circuit from mechanical stress, such as impacts or from contaminants (impurities, moisture), thereby creating a barrier against those harmful substances coming from the external environment.
The so-called final passivation typically includes a relatively thick layer completely covering the device to protect it. However, at the edge of the device the presence of the final passivation alone is not sufficient to ensure its sealing. Other measures are necessary. Primarily for this purpose, the most peripheral structures of the device are typically left inactive, i.e. disconnected electrically from the device terminals.
More specifically, for protection of the device at the edges there is formed a structure arranged peripherally which also permits sealing of the device. This is a device edge morphological structure and reference will be made thereto in the following description. It includes a closed ring completely surrounding the device along its entire periphery. This structure is known to those skilled in the art as Chip Outline Band (COB), i.e., a band surrounding the device.
The device edge morphological structure is formed simultaneously with the electrical structures of the integrated circuit. The more internal part of the COB, i.e. the part nearest the device, does indeed normally include structures which appear morphologically identical to the electrically active ones of the device. Moreover they do not have any electrical function since they are electrically insulated, but only act as termination for the device. The COB structure is consequently different in different devices depending on the process used and the device design.
In any case the most external part of the COB, which terminates in the scribe line adjacent to and is contiguous with the preceding part, is designed so as to completely seal the device from the external environment. For this purpose there is applied the simple principle in accordance with which to permit better sealing each overlying layer must be terminated further externally than the one immediately below. The layers are disposed to virtually cover back each other. This way the edge descends gradually downward while going near the associated scribe line, such as to enclose the integrated circuit several times in subsequent shells.
An example of a device edge structure of the known type is shown in FIG. 1. Specifically, there is represented in cross-section, not to scale, a peripheral portion of a single device. By way of example the device is of the type formed by a CMOS process with two polysilicon levels. In particular, reference is made by way of example to a device, such as a non-volatile memory typically of the EEPROM or FLASH type.
In addition, the device comprises specifically two interconnection levels. Indeed it should be remembered that two or more interconnection levels are typically provided in the more complex integrated circuits to limit the area occupied by reducing the size of the components, and, thus, of the device to thereby increase the total number of devices which can be integrated on a single wafer.
The device has been sectioned from the interior to the exterior along a line parallel to an edge. In particular, the section line passes along a source-drain line of memory cells. In FIG. 1 the visible portion of the device edge morphological structure is indicated as a whole by reference number 1. Further to the right of the figure is seen a scribe line of which the visible part is indicated by reference number 2. On the left the device edge morphological structure joins the active part of the device i.e. the actual electronic circuit (not shown in FIG. 1) of which it defines an extension with continuity. It should be remembered that the device edge morphological structure is shown in its most peripheral region, while in some cases another portion thereof comprising other electrically inactive structures could be present at the device periphery.
In FIG. 1 for greater clarity the COB is divided approximately and ideally into two regions as set forth above. A region indicated by reference number 3 is placed more internally with respect to the circuit and comprises structures morphologically identical to those of the circuit, but not electrically active and providing a sort of extension with continuity of the device circuit structures, and a region 4 which is more external or peripheral having a structure which more correctly has a device sealing function.
The device is formed in a major surface 5 of a substrate 6 of monocrystalline silicon. The process calls for simultaneous formation of the actual circuit and its edge morphological structure. Primarily on the major surface 5 are formed so-called field oxide insulation regions which are indicated by reference number 7 and define active area regions 8.
Internally to the active area are then formed the circuit structures, such as transistors and memory cells, i.e., floating gate transistors. In region 3 and in particular at the left termination of FIG. 1 is visible a structure similar to that of a memory cell along the source-drain direction and indicated as a whole by reference number 9.
The process for forming the circuit components comprises schematically the following steps:
growing in the active area regions a thin tunnel oxide, indicated by reference number 10, for the memory cells and which at the end of the process will remain in the structure of the floating gate transistors; PA1 forming a first polysilicon layer 11, briefly Poly1, over the entire structure; PA1 defining this first layer in a direction parallel to the source-drain lines in the memory cells to delimit the floating gate in that direction; PA1 growing or depositing an interpoly dielectric layer 12; PA1 removing by masking with a mask known as a "matrix" and etching the interpoly dielectric, the Poly1 and the tunnel oxide in the regions outside the memory cells matrix; PA1 growing a thin gate oxide layer in the active area regions where there will be formed the transistors possibly, inside the matrix or in the external circuitry part; PA1 forming a second polysilicon layer or Poly2 and typically also a silicide layer over the entire structure. The layer indicated by reference number 13 represents alternatively a single layer of Poly2 or a polycide layer formed by superimposing polysilicon and silicide; PA1 defining a mask typically known as a matrix definition mask and following etching Poly2/interpoly/Poly1 in the matrix in a direction perpendicular to the source-drain direction for definition of the memory cell structures only in the matrix region; and PA1 defining the Poly2 layer only in the circuitry regions outside the matrix to define the structures, i.e., the transistors of the circuitry.
In the structure 9 is visible the floating gate formed by Poly1 and the control gate provided by Poly2. Beside the transistor gates are then formed oxide layers known as "spacers" 14 to insulate them. Once the structures of the electric circuit components have been completed, a so-called "intermediate" dielectric layer acting as their insulation is formed above. In the figure can be seen the portions, indicated by reference number 15, of this layer which are included in the device edge morphological structure 1. Conventionally the intermediate dielectric comprises a layer of Boron Phosphorus Silicon Glass (BPSG), i.e., of silicon oxide doped with boron and phosphorous.
Then one proceeds to formation of the electrical connections. But the transistor 9 being within the device edge morphological structure 1 will not be connected electrically to the device terminals. For formation of the connections, in the intermediate dielectric there are opened appropriate holes to the surface 5 of the substrate to allow contact therewith by overlying conducting levels. A first interconnection level, i.e. a metallization layer, typically aluminum, more briefly known as "METAL 1", is overlaid on the intermediate dielectric 15. The first metallization layer is indicated by reference number 16 and has portions in direct contact with the surface 5 through the above mentioned holes, denominated contacts. More correctly the term contacts will be used to designate those regions at openings in an interposed dielectric layer through which is provided electrical contact between METAL 1 and the substrate or METAL 1 and the circuit elements. In FIG. 1 the contacts between METAL 1 and the substrate are indicated by reference number 17.
The metallization layer 16 is then patterned so as to have the appearance of metallic strips. As shown in FIG. 1, in this embodiment the most external termination or peripheral termination 18 of the METAL 1, which is located in region 3, is placed above the intermediate dielectric 15.
Over the first interconnection level 16 is formed a multilayer of dielectric material to insulate it from a subsequent second overlying metallization layer or briefly "METAL 2" indicated by reference number 19. In the description given below reference is made to this multilayer as to an intermetallization dielectric multilayer or intermetallization dielectric because it is placed between two metallization layers.
The intermetallization dielectric is indicated as a whole by reference number 20 and also acts as a planarizer of the surface before formation of the second metallization layer 19 to ensure a deposition and a definition thereof without drawbacks. Indeed, after formation of the METAL 1 layer the surface of the resulting process structure displays a sort of stepped profile due to the presence of the structures of the electrical component and of the first metallization level.
As shown in FIG. 1, to planarize the surface of the underlying structure, the intermetallization dielectric 20 includes a layer of Spin-on Glass (SOG) which as known is commonly used for planarizing in various steps of the formation of the integrated circuits. This is an amorphous material which is deposited in the fluid state, as a solution, by means of a "spinning" process, i.e., being sprayed over the entire surface of the wafer where it is deposited in such a manner as to flow towards the deeper zones. The latter are accordingly filled and the irregularities of the underlying structure smoothed. After hardening by evaporation of the solvent, a following anisotropic etching of the SOG leaves its top surface virtually flat. The etching is stopped when the relatively higher zones of the underlying structure are completely exposed.
It should be remembered however that the SOG, since it is a highly contaminating material because of its origin, must be enclosed between insulating layers so as not to come into contact with the active structures of the circuit. Specifically, as shown in FIG. 1, the intermetallization dielectric 20 then includes a first layer consisting of a silicon oxide, typically TEOS (tetraethylorthosilicate) indicated by reference number 21, a layer of SOG 22 and a second layer of TEOS 23. The TEOS is chosen preferably because it has good chemical and physical characteristics and is a material which does not introduce contamination.
In accordance with the prior art process the first TEOS layer 21 is arranged conformal to the underlying structure and accordingly displays a profile which is still not planar. Formation of SOG in accordance with what has already been mentioned, so as to fill only the deepest portions, permits planarizing of the surface. In this manner, after the conformal deposition of the second TEOS layer 23 there is obtained a virtually planar surface for deposition of the second interconnection level 19. Following its formation, holes are opened in the intermetallization dielectric 20 by means of masking, these holes permitting formation of the so-called VIAs for contact between METAL 2 and METAL 1.
As may be seen in the figure, in region 4 of the device edge morphological structure 1 the intermetallization dielectric 20 is terminated outside the termination 18 of the first conducting layer 16, in accordance with the principle set forth above to ensure good sealing of the device. In accordance with a prior art technique, formation of the peripheral termination of the intermetallization dielectric multilayer takes place simultaneously with formation of the openings of the VIAs in the intermetallization dielectric 20, i.e. by using an opening in the same mask.
FIG. 1 shows a single VIA 24 in region 3 of the edge morphological structure 1. The intermetallization dielectric is therefore discontinuous since it is separated in two portions with one being included in region 3 and the other extending into both regions 3 and 4 of the morphological structure 1. On this subject it should be remembered that formation of the contacts, which allow connection between a metallic interconnection and the substrate or circuit components, and of the VIAs between conducting layers of different levels is very critical in very large scale integration manufacturing processes because of the extremely small cross-sectional dimensions which they must have, and of the relatively large thickness of the dielectric layer through which the holes must be made. Under these conditions, during sputter deposition of the metallization layer which will form the contact, the cover of the vertical walls of the "holes" becomes unsatisfactory and the metal deposited can display unacceptable thinning. On the other hand it is not possible to reduce the thickness of the dielectric layer, and, hence, the depth of the contact proportionately to the cross-sectional dimensions. A common attempted approach uses for the metallization portion which is to be inside the "holes", a metallic material, typically tungsten, titanium and/or titanium nitride, which can be deposited by chemical vapor phase deposition to allow easy filling of the hole.
In this direction there was developed a technique according to which the "holes" are first filled with tungsten plugs. The aluminum layer is then deposited so as to form the conducting layer. Techniques of this type are described, e.g., in the articles, "Selective CVD of tungsten and its applications to MOS VLSI" by Takahiko Moriya and Hitoshi Itoh, VLSI Research Center, Toshiba Co., presented at the Workshop 1985 of the Material Research Society; "A study of tungsten etchback for contact and VIA fill applications" by Jen-Jiang Lee and Dennis C. Hartman, presented at the IEEE VLSI Multilevel Interconnection Conference (VMIC), 1987.
More specifically in accordance with a process to which specific reference is made in the following embodiments of the present invention, for the formation of the contacts and the VIAs in the holes there is first deposited a pre-adhesion or barrier layer. Typically the barrier layer comprises a first layer of titanium (Ti) on which is deposited a second layer of titanium nitride (TiN) (together Ti/TiN) for a total thickness varying between 50 nm and 90 nm. On the barrier layer a tungsten layer is then deposited by the CVD technique. A subsequent etching leaves the tungsten only in the holes in the form of plugs. This technique is described for example in European patent application no. 0543254 to the assignee of the present invention. An improvement of this technique is described in European patent EP 0571691 also assigned to the present assignee.
In FIG. 1 the barrier layer Ti/TiN is indicated by reference number 25 and the tungsten plug by reference number 26. It is noted that, since the process calls for the peripheral termination of the intermetallization dielectric 20 to be created by means of a mask for formation of the VIAs, a tungsten residue is also present in the zone of the above mentioned termination. As may be seen in the figure, since an anisotropic etching is used, after partial removal of the tungsten for formation of the plugs a so-called tungsten bead, indicated by reference number 27, and an underlying very thin barrier layer 25, accordingly remain beside the above mentioned termination.
The second interconnection level 19 terminates towards the surface 5 of the substrate further out than the termination of the intermetallization dielectric multilayer. In particular, as discussed below, it is in contact with the intermediate dielectric layer 15. A relatively thick final passivation layer, indicated by reference number 28, completes formation of the device by providing protection of the circuit elements and the interconnection levels.
To allow separation of the devices provided on the same wafer, the final passivation layer is then etched in the scribe line region, i.e., in region 2, until reaching the substrate surface 5. The scribe line has been formed at this step. FIG. 1 shows the device as it appears at the end of this step.
The process for formation of the device edge morphological structure 1 just described concomitantly with the electrical circuit formation process and illustrated in FIG. 1 displays, however, some drawbacks which appear evident from an analysis of the structure 1 obtained. It should be is noted that normally the SOG, in accordance with the conventional planarizing process with three layers diagrammed above, is completely enclosed between dielectric material layers. This is visible even in FIG. 1 in region 3 of the device edge morphological structure, i.e., as concerns the intermetallization dielectric portion 20 placed more internally, to the left of the VIA 24.
However, as shown in FIG. 1, in accordance with the process for the formation of the device edge morphological structure in accordance with the prior art in the more external portion of the intermetallization dielectric multilayer 20, placed to the right of the VIA 24 and extending with continuity between the two contiguous regions 3 and 4, the SOG is not completely incorporated. Indeed, the intermetallization dielectric 20 in region 4 of the morphological structure 1 is in a zone placed with respect to the surface 5 at a level relatively low in the structure as obtained in the process step preceding formation of the intermetallization dielectric 20. In particular, indeed this zone is lower than the first metallization layer 16. In this zone the SOG is accordingly present. The terminal etching of the intermetallization dielectric multilayer 20 immediately outside the end of the first interconnection level 16 is formed by etching the SOG layer 22.
Accordingly, the SOG terminal portion is not insulated from the second metallization layer 19 which ends more peripherally to cover the intermetallization dielectric, but instead is in contact with the tungsten bead 27. The presence of SOG exposed to the next metallization layer 19 can give rise to defects. In a certain percentage of devices there may occur delayering of the overlying metallization level.
As known to those skilled in the art, each SOG layer, if it has not been perfectly cured, may shrink before formation of the next metallization layer. The behavior of this material is due to a natural phenomenon known as outgassing. The problems of defects connected therewith when the outgassing occurs at the interface with a metallization layer, as in our case, are illustrated for example in the article of C. Chiang, N. V. Lam, J. K. Chu, N. Cox, D. Fraser, J. Bozarth, B. Mumford, entitled "Defects study on spin on glass planarizing technology", Proceedings Conference VMIC, 1987; and in the article of M. Kobayakawa, A. Arimatsu, F. Yokoyama, N. Hirashita, T. Ajioka, entitled "A study of outgassing from spin-on-glass films used for planarizing", Proceedings Conference VMIC, 1991. As analyzed in these articles, the outgassing also leads to formation of structural defects in the metallic layers in contact with the SOG.
In addition, in the process just described and illustrated, the presence of the tungsten bead in contact with the SOG enormously worsens the problem. As shown in FIG. 1 the SOG layer 22 when shrinking inwardly, before formation of the barrier layer Ti/TiN 25, leaves an empty space indicated by reference number 29 between the outermost edges of the two dielectric layers 21 and 23. The side surface of the termination of the intermetallization dielectric 20, obtained after cutting of the dielectric and which must be covered by the second interconnection level, because of the SOG shrinkage is accordingly irregular and has a negative slope.
This induces a stress in the barrier layer 25. To this is added the fact that the thickness of the barrier layer 25 is much reduced as described above and is deposited by an anisotropic technique and therefore on such a negative step it is thinned, i.e., it does not have uniform thickness, and can even be missing at some points. For these reasons delayering of the barrier may occur, i.e., partial lifting thereof along the contact with the termination of the intermetallization dielectric.
The tungsten layer formed at this point is deposited both outside and inside the lifted edges of the barrier layer 25. It should be remembered that tungsten has high stress, and that during a common process for forming tungsten, tungsten fluoride is typically used as a source. This highly corrosive gas is able to penetrate any holes present in the barrier layer. The tungsten etching necessary for formation of the plugs thus generates a highly defective structure. The following metallization layer 19 can accordingly be delayered, differently from how it appears in the ideal case shown in FIG. 1.
The device can be damaged in case of marked delayering in which there can be generated on the surface of the wafer residues of delaminated layers which cause short circuiting of active metallizations. Alternatively such a defective structure, which since it is a device edge morphological structure is not electrically active, may not immediately damage the functionality of the device, but which once operating would become clearly unreliable in a more or less short time because it is not correctly sealed. The problem described is accentuated in the devices located near the wafer edge, in which the barrier layer is thinned because it forms a meniscus upon deposition.
Another drawback can occur in the known device edge structure shown in FIG. 1. It can be observed that the intermediate dielectric layer 15 of BPSG located to the right of the most external contact 17 does not display discontinuities, extending from the contact 17 to the scribe line 2. During opening of the VIAs for formation of the contacts between the two metallization layers 16 and 19 the peripheral multi-etching of the intermetallization dielectric 20 forming the termination of the multilayer 20 in fact continues in part towards the underlying intermediate dielectric 15. The intermediate dielectric 15 should be entirely removed, but as shown in the figure it can be etched only partially due to process marginality. At the end of the etching accordingly a layer of BPSG of reduced thickness remains underneath the bead 27. Thus a continuous layer of BPSG is left between the contact 17, i.e. between the METAL 1 and the outside with resulting reliability problems. The BPSG represents in the known structure a continuous path for entry of moisture toward the first interconnection level. As known indeed the chemical reaction between BPSG and moisture produces phosphoric acid which can corrode the metallization layers.
On the other hand, totally avoiding etching the intermetallization dielectric inside the device so that it may extend to the scribe line is not a possible solution to the problems discussed, because there would remain a SOG part exposed to the scribe line, and hence, to the external environment with a resulting lack of insulation of the device because of the high hygroscopicity of the SOG.
The problem illustrated accordingly seems insoluble. Indeed, good sealing is prevented for any device in which SOG is to be used as the planarization layer because of the presence of at least one subsequent metallization level. The same problem arises both in the framework of a intermetallization dielectric for a device having at least two interconnection levels, and in a case not specifically described in which the SOG is already used in the intermediate dielectric for devices having a single metallization level and in which inside the intermediate dielectric there are to be formed contacts for the first metallization level.
It should be noted that although the drawbacks described are discussed for the case exemplified in FIG. 1 they can appear every time a dielectric having similar characteristics, such as an amorphous planarizing material highly contaminating especially for the metallization layers and capable of generating defects, is used for the planarizing instead of SOG. In addition these shortcomings are very devastating when the contacts and the VIAs are created by means of the described plug technique.
There thus exists a need to conceive a process for formation of a device edge morphological structure allowing perfect sealing of the device even when planarizing materials such as SOG are present. On the other hand the process must not entail an increase in complexity with respect to a conventional process with the addition of dedicated process steps.